1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched DMOS power transistors. More particularly, this invention relates to a novel and improved structure and process for fabricating a trenched DMOS power transistors manufactured without requiring a source mask and provided with specially configured trench edge source extension to shortened source regions wherein the risk of turning-on a parasitic bipolar transistor in the DMOS transistor is reduced and more reliable source contacts are provided.
2. Description of the Prior Art
As the width of the source regions are shortened to provide a special advantage of preventing an incidental turning on of the parasitic PN junctions, the narrowed source regions however generate a different technical difficulty that reliable source contacts cannot be conveniently formed due to the very small areas above the source regions with shortened width. The advantages provided by the narrower source regions cannot be practically realized due to the difficulties created by this limitation.
For semiconductor power devices, such as DMOS or IGRs, there are inherent concerns of the incidental turning-on or incipience of current conduction in a parasitic bipolar transistors in these type of devices. Partial or total loss of current control may be resulted from such incidental turning on events. Potential damages to the device or even complete destruction can be a sequence of such undesirable situations. Prevention measures are therefore required to circumvent the occurrences of such events in order to increase the ruggedness of the device. A typical prior art technique to prevent parasitic transistors from turning on is to provide "electrical short" or low resistance connection between the adjoining source and the base regions thus preventing the forward biasing above a threshold level of a P-N junction between them. In order to assure that no part of the P-N junctions is excessively forward biased, the distance between the short and the furthest part of the P-N junction, which generally is the width of the source region, should be minimized. Conventional method of device manufacture typically produce semiconductor devices with a source region which have width ranging from few micrometers to ten micrometers. Such widths are generally not satisfactory for the purpose of preventing the parasitic P-N junctions from being incidental turned on.
For a conventional fabrication method, the width of the source regions cannot be reduced beyond certain limits. These limits are imposed due to the precision limitations of mask alignment. First, the potential misalignment of source contact mask for opening contact windows above the narrow source regions impose a requirement that the contact windows have to be larger in size to assure direct contact with the narrow source region under a worst misalignment situation. However, a large contact window raise another concern that the source contact metal may incidentally contact the trench gates causing a short thus leading to a device malfunction. Due to these concerns, the source regions are required to maintain certain minimum width to compensate for potential errors caused by contact mask misalignment. Furthermore, for smaller size of source regions, a very stringent requirement on alignment is imposed on the trench etching windows. Due to the difficulty that the source regions and the trench gates are not self aligned, it is very difficult to precisely align the source regions relative to the trench gates. For this reason, the source regions cannot be made with further reduced size in order to accommodate trench mask misalignment errors. Thus, according to the conventional manufacture method, the width of the source regions cannot be reduced beyond certain limitations.
In order to overcome this difficulty, in U.S. Pat. No. 4,567,641, entitled "Method of Fabricating Semiconductor Devices having a Diffused Region of Reduced Length" (issued on Feb. 4, 1986), Baliga et al. disclose a semiconductor device having a diffused region of further reduced length by applying a different manufacture method. In this semiconductor device, e.g., MOSFET, a N+ source region is diffused into a P-base region through a window of diffused mask. An an-isotropic or directional etchant is applied to the N+ source region through the same widow. The etchant removes most of the N+ source region but allow the shoulder of the source region to remain intact. The remaining shoulder regions now become the source regions, having a reduced diffusion length thus greatly reducing the risk of turning-on a parasitic bipolar transistor in the MOSFET transistor.
The method of fabrication and the device structure of the MOSFET transistor as that disclosed by Baliga et al. cause another difficulty. The shortened source region allows very limited areas for the source contact. In order to overcome this difficulty, special arrangements are made to provide tunnel junction as low resistance contact between the source region and the source contact as that shown in FIG. 1. In this MOSFET 80 by Baliga et al., a P+ region 58 is provided to complete an electrical short between the P-base 56 and a N+ source region 66. The electrical short consists of three components. A first component is a junction 82 between the P region 58 and the N+ source 66 where a tunnel junction 82 is formed because each of these regions are heavily doped, e.g., each region are doped with 10.sup.19 dopant atoms per cubic centimeter of silicon. The tunnel junction 82 constitutes a low resistance connection between the N+ source region 66 and the P+ region 58 during normal device operation. The second component of the electrical short is provided at a location E includes a the junction 84 between the P-base 56 and the P+ region 58. The junction 84 constitutes a low resistance path between the P-base 56 and the P+ region 58 because the holes can freely pass from the P-base 56 to the P+ region 58. The third component of the electrical short at the location E includes the P+ region 58, in the vicinity of location E, between the tunnel junction 82 and the junction 84. This is because the region 58 is highly doped and thus constitutes a low resistance path between the junctions 82 and 84. All these three low resistance paths collectively provide a low resistance path between the P-base 56 and the source region 66.
The device structure of providing an electrical short by combining three components of low resistance paths is very complicate and therefore difficult to control the quality of the electrical paths with predictable resistance. Very accurate control of many parameters during the fabrication process are required in order to assure good quality low resistance electrical paths are achieved for this kind of device structure. The device as disclosed by Baliga et al. may appear advantageous in theory but practically, such a device may be too complicate for actual implementation. Furthermore, the resistance between the source metal and the N+ source is high, especially when the drain to source voltage V.sub.DS is small. Such a device may become difficult to switch for a low on-resistance power MOSFET device.
Therefore, there a need still exits in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties. Specifically, it is desirable that shortened source regions can be manufactured on the semiconductor while direct and reliable source contact can also be formed with simplified manufacture processes such that power transistors of increased ruggedness can be manufactured with reliable performance without unduly incurring increased production costs.